RoboSemi Platform Docs
Deep technical documentation with expandable specs for every technology area — VLSI, AI/ML, IoT, Cloud & Security.
VLSI Design
Enabledv1.4Silicon to System — Full Custom IC Design Flow
Complete RTL-to-GDSII flow using industry-standard EDA tools and verified IP cores. Supports 7 nm to 180 nm process nodes. Click any item below to expand full technical specifications.
Full Design Flow (RTL → GDSII)
Click any step to expand detailed tool, constraint, and sign-off information.
Supported Process Nodes
Click any node card to see full electrical and physical specifications.
Verified IP Core Library
Click any IP core to expand full performance specifications and interface details.
Features & Status
Behavioural and structural RTL in SystemVerilog with full lint, CDC, RDC checks via Synopsys SpyGlass.
Synopsys Design Compiler / Cadence Genus with MCMM timing sign-off via PrimeTime.
Cadence Innovus + Synopsys ICC2 — hierarchical floorplan, CTS, detailed routing, DFM fill.
Mentor Calibre sign-off against foundry decks. Zero waivers policy for tapeout.
Cadence Spectre / HSPICE + Calibre xRC parasitic extraction + SDF back-annotation.
JasperGold property checking — SVA assertions, model checking, RTL vs. netlist equivalence.
Quickstart
- 1Define specs: process node, voltage, frequency target, area budget
- 2Write RTL in SystemVerilog; run lint with SpyGlass (0 errors)
- 3Synthesize with DC targeting PDK std cells (MCMM sign-off)
- 4Run PnR in Innovus; close timing: hold/setup margin ≥ 0.1 ns
- 5Run Calibre DRC + LVS; achieve 0 errors before GDSII export
- 6Submit GDSII + LEF/DEF package to foundry for tapeout